Complete Communications Engineering

The following table details performance numbers for a number of specific RS (n, k) implementations for two general purpose processing architectures and one digital signal processor. Numbers are provided for both decode in the presence of no error, as well as decode in the presence of maximum channel error. Note that correcting errors requires more processing power than simply validating blocks, and that the required processing power increases linearly with the error rate. Typical applications tend to keep the error rate low such that active correction is not required.

The two digit hexadecimal number in each column specifies the GF(255) primitive polynomial used to generate the underlying Galois field.

The listed performance numbers are:

  • CPB – Cycles Per Block, how many cpu cycles are required to perform this step of the algorithm for each block of data, and
  • MBPS @ 1GHz – maximum throughput in MBits/sec for each 1.0 GHz of processing power (bit rate measured on the data side, not the channel side.)

All measurements are for optimized C code for the particular architecture, compiled with GCC and -O4 optimizations. No hardware acceleration or SIMD instruction optimizations were used.

Table 1 - x86

Table 2 - ARM 920T

Table 3 - TI C5502